The present invention pertains in general to battery-backed integrated circuits, and particularly to CMOS battery-backed integrated circuits and to circuits therein which prevent battery leakage due to parasitic PNP transistors.
Recent years have seen an increased use of integrated circuits which are "nonvolatized" by providing a small power supply to maintain their data state. Such arrangements have many advantages, including cost and compatibility. For example, the battery-backed memories available from Dallas Semiconductor typically include an SRAM and a tiny lithium battery in a single module, which has standard DIP pinout. If the external (system) power supply fails, the battery will provide enough voltage to retain data in the memory until system power is restored. Such a nonvolatized memory module will typically be cheaper per bit than an EEPROM module, and will have the further advantage of 100% compatibility with the functional specifications of a standard SRAM. For example, EEPROMs are very slow to write. Such nonvolatizing techniques have also been used to provide power-fault survivability in microprocessors, clock/calendars, and other types of integrated circuits.
In battery-backed systems, the battery voltage is typically lower than the operating supply voltage. For example, the battery voltage may be approximately three volts, whereas the operating voltage is five volts. In order to prevent current from the power supply flowing into the battery and thus charging the battery, a PN diode is utilized that is reverse biased in the normal operating mode. When non-rechargeable batteries (such as lithium batteries) are used, battery charging may damage the batteries.
Such a battery protection diode is typically realized with a P-well formed in an N-type substrate. The battery is connected to the P-well, so that it can source current to the N-type substrate when the operating supply voltage is not connected. The N-type substrate is then operable to be connected to the operating supply voltage that is higher than the battery voltage. Thus, when the operating supply voltage is connected, the diode is reverse biased.
One problem that occurs in the diode protection system is caused by the action of a parasitic PNP transistor when the battery is sourcing current. This parasitic PNP transistor is formed by an adjacent P-well device in the N-type substrate that is connected to a voltage lower than the battery voltage, resulting in a reverse biased PN junction. Whenever the adjacent P-well device is connected to a voltage lower than the battery voltage and the external supply is not utilized, current can conduct through the substrate to the adjacent P-well device through this parasitic transistor. This is the result of minority carriers injected into the substrate from the forward biased PN junction of the battery protection diode and collected in the adjacent P-well. This leakage current therefore provides an unexpectedly high drain on the battery, thus reducing its lifetime and the lifetime of the battery backed-up product.
The present invention provides improved battery-backed integrated circuits, which include improved battery protection circuits for preventing battery charging. The battery power input is connected through a first junction diode, so that the battery cannot be charged when the external (system) power supply is active. The battery isolation diode is surrounded by a second junction. The second junction is preferably shorted out, by a wired connection which makes ohmic contact to the semiconductor regions on both sides of the junction. The built-in potential of this junction provides efficient collection of minority carriers, which will recombine in the neighborhood of this junction. Thus, the second junction collects the minority carriers which can be generated when the first junction is forward biased (i.e., when the integrated circuit is being powered from the battery). Otherwise, minority carriers could diffuse to other junctions, to cause leakage currents which can significantly degrade the lifetime of a low-powered device.
In the embodiments which are presently most preferred, two slightly different structures are used: one for integrated circuits which have N-type substrates (or analogous structures), and the other for integrated circuits which have P-type substrates (or analogous structures). (However, either class may also be adopted for use in a wide variety of other structures.)
In most CMOS circuits with N-type substrates, normal circuit function requires that the N-type substrate be held at the positive power supply voltage. Thus, in a battery-backed system, when the external power supply fails, the battery voltage provides power (V.sub.DD) to the active circuits, and holds up the substrate voltage. The substrate voltage will define the voltage of the N-wells (where the PMOS devices of a CMOS integrated circuit are located). (The N-wells may be a part of the substrate, or may be separated from it by at most a high/low junction.) If the voltage of the N-wells were allowed to float, some of the PMOS devices might turn on or turn off improperly, or exhibit anomalous leakage, and thus a stored logic state could be lost.
By contrast, in most CMOS integrated circuits with P-type substrates, the P-type substrate is held at ground, and there is no need for the battery to hold up the substrate potential. However, in this case each of the various N-well regions (separated by P-type substrate) must normally be pulled up to the positive supply voltage during normal operation.
A significant device-level feature, in integrated circuits according to some embodiments of the invention, is the provision of an intermediate-depth diffusion. This intermediate-depth diffusion will have a junction depth (inside the P-well or N-well) which is significantly deeper than the source/drain junction depth, but significantly shallower than the depth of the well. This intermediate-depth diffusion is useful in the innovative diode structure described, but can also be used for other device structures. For example, this structure provides a compact bipolar transistor structure with reasonably high gain. This intermediate-depth diffusion can also be used for input protection structures (i.e. to provide device structures which will rapidly and recoverably break down, when a high-voltage pulse appears, to discharge the high-voltage pulse without damaging the primary circuitry of the chip). For another example, this intermediate-depth diffusion can also be used to form diffused capacitors with relatively large capacitance per unit area, or capacitors whose capacitance varies greatly with voltage (such capacitors are commonly referred to as varactors.)
A further advantage of this structure, and a further innovative teaching set forth herein, is that the innovative structure can be fabricated with minimal added process complexity. An intermediate-depth diffusion is added to a standard process flow; but the shallow diffusions in the battery protection structure simply make use of the source/drain implants, and the deepest diffusion simply uses the N-well (or P-well) fabrication steps.
For process, simplicity, the intermediate-depth diffusion is most preferably formed by using an implant which is identical (in dose and energy) to another implant used in the same process. The additional junction depth is achieved by exposing the earlier implant to a high-temperature step before the later implant is performed, so that the earlier implant will have a correspondingly greater diffusion length (integral (Dt).sup.0.5).
A variety of "substrate" structures are commonly used for integrated circuits, and far more have been proposed or have seen limited use. For example, the "substrate" which surrounds the N-wells and P-wells is often an epitaxial layer atop a much more heavily doped underlying layer. For another example, the N-wells and P-wells are commonly formed by separate implantation (and drive-in) steps, and such processes are referred to as "twin tub" processes; but alternatively one of these steps may be omitted, so that, for example, the PMOS devices might be formed directly in an N-type upper substrate portion. Other important structure types include silicon-on-insulator structures and full dielectric isolation structures, where there is no electrically continuous body linking all of the wells. It is important to note that the innovative teachings set forth herein can advantageously be adapted to a tremendous variety of substrate structures, including not only the embodiments listed or mentioned, but also many others.
It should be noted that the disclosed families of devices structures can also be used for a variety of other purposes. In particular, the disclosed structure provides a diode structure which may be adapted for use in other types of device structures, in very-low-power integrated circuit applications.
It should also be noted that some prior art CMOS structures have used guard ring structures to suppress latchup. The problem of latchup (suppressing the parasitic thyrsistor) is a guide different problem from the leakage problems discussed above, but in both cases collection of minority carriers is desirable. Guard ring structures are commonly used to surround locations (such as output drivers) where transient signals are most likely to cause injection of minority carriers. (A sufficient injection of minority carriers could fire the parasitic thyrsistor, and thus lead to latchup.)
In another class of embodiments, the innovative diffusion structure described is used in a different way. In low-power battery-backed integrated circuits, every current drain must be minimized, to conserve the charge in the battery. One drain on the battery is caused by negative excursions on an incoming data line (for example, when a negative voltage spike occurs due to an electrostatic discharge (ESD) event. In a normal battery-powered integrated circuit, the current drawn during such a negative voltage surge would be drawn both from the ground connection and also from the power supply connection. However, in stringently power-limited applications, even this amount of current, over the lifetime of the part, can use enough of the battery capacity to shorten the part's lifetime substantially.
That is, when a negative transient occurs, a large number of electrons will be injected. If these electrons are allowed to diffuse freely, many of them will diffuse toward the high-potential regions which are connected to the battery. This charge transfer reduces the total charge available during the lifetime of the battery.
The shielded diode structure of FIG. 8 is protected: almost all electrons injected at first junction 111 will be collected at second junction 112. By contrast, a simple FET output driver, like transistor 150 in FIG. 10, is not isolated: when the drain junction of such an NMOS FET is forward biased, electrons will be released into substrate 140, and many of these electrons can then diffuse to regions of high potential.
Therefore, a further innovative teaching is to use the innovative diffusion structure to source current to negative transients which may occur on the I/O lines of a chip. In this embodiment, an I/O line is connected so that the first junction (in a structure as described above) will be forward biased when the I/O line goes negative, and the other side of the first junction is connected to ground potential. Thus, when a negative-going transient occurs, current will be sourced, through the first junction, from ground.
When a negative-going transient occurs, some current will also be sourced, at the output transistor which drives the I/O line, and some of this current component will cause minority carrier diffusion; but the use of this innovative teaching helps to reduce the amount of current sourced which can cause minority carrier diffusion. Preferably the area of the first junction is substantially larger than that of the junction area of the source/drain diffusion, in the output transistor, which is connected to the power supply.
This innovative teaching also has two further advantages. First, the reduced risk of minority carrier injection means that the risk of stored data states being upset by transient signals is reduced. Second, the risk of latchup is reduced.
Thus, this innovative teaching advantageously provides a battery-powered integrated circuit which is protected against battery depletion by electrical noise appearing at input/output connections. This innovative teaching may be particularly advantageous in integrated circuits which are intended for use in systems where high levels of noise must be tolerated.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a position backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the first region includes a shallow heavily doped P-type diffusion, at the surface thereof, which runs substantially parallel to the first junction for the whole length of the first junction.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-wall regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the third region includes a shallow heavily doped N-type diffusion, at the surface thereof, which runs substantially parallel to the first junction for the whole length of the first junction.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the third region includes a shallow heavily doped N-type diffusion, at the surface thereof, which runs substantially parallel to the second junction for the whole length of the second junction.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the second region is completely enclosed, except for a surface for ohmic contact, by the first region.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the integrated circuit is formed in an epitaxial semiconductor layer on a monocrystalline semiconductor body.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the N-channel transistors are formed within P-well regions which are more heavily doped than the extended region.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defining a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; whereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the N-channel transistors are formed within the extended region.
Among the innovations disclosed herein is an integrated circuit, comprising: an extended region of P-type monocrystalline semiconductor material; a plurality of N-well regions within the extended region, and a plurality of P-channel field-effect transistors formed in ones of the N-well regions; a plurality of N-channel field-effect transistors formed in portions of the extended region; a power terminal, for connection to a positive external power supply voltage, the power terminal being operatively connected to ones of the N-well regions; a battery terminal, for connection to a positive backup power supply voltage, the battery terminal being connected to ones of the N-well regions through a structure which includes: a first region which is P-type and which is connected to the battery terminal; a second region which is N-type and which is surrounded by the first region, the first and second regions defining a first junction therebetween; and a third region which is N-type and which surrounds the first region, the first and third regions defined a second junction therebetween, the second junction surrounding the first junction; the first and third regions being ohmically connected to each other; thereby minority carriers which are injected in the vicinity of the first junction will be collected at the second junction; wherein the first region is more heavily doped than the third region.